:: How to Make Sense of the DFM/DFY Maelstrom

By: Andrew B. Kahng

Having served as technical advisor to a number of semiconductor and EDA companies, and having also recently founded a company focused on delivering DFM solutions to the semiconductor industry, I'm often asked what the CTO of a semiconductor company should consider when evaluating the myriad DFM/DFY startup offerings.

The first question the CTO must consider is: "How can DFM/DFY help me?" In other words, is DFM/DFY even an issue for his business? If the CTO can meet competitive requirements (power, timing, cost, time to market) with a mature, safe process (>= 130nm) then there may be little need to worry about DFM/DFY outside of whatever is provided in standard reference design flows. Otherwise, the CTO must decide whether EDA technology, process technology, and his design all converge at the right point in time, with the right risk-benefit profile.

Rigorous ROI analysis must be performed for DFM/DFY, particularly if a solution is new and unproven. The initial validation and production qualification can be very expensive - $2-3 million for masks, processing, measurement, engineering resource and schedule hit for any silicon validation. This will not be practical for anything but a very high-volume part, or a truly 0-1 value proposition - i.e., the DFM/DFY tool shifts the design from economically infeasible to economically feasible.

With so many new tools and methodologies coming on-line, the CTO must verify the committed timeline for foundry support and process maturity of the right process flavor. Cost of adoption (licenses, flow integration, training, support), impact on schedule (both adoption and in production), disruption to tapeout schedule, etc. must all be weighed against hoped-for gains in time-to-volume or cost.

It is also important to consider technology and business risks on the EDA side. The CTO must consider whether the DFM/DFY solution requires foundry data, tool interfaces or design subflows that aren't yet available and proven - and whether the provider's financial stability and product silicon collateral pass muster. The bar is high for startup tools not only because of such business risks: having a unique value proposition, and offering tool robustness and interoperability, are required to win over design and CAD teams who wish to limit the number of distinct EDA providers in the flow.

The second question the CTO must answer is: "Which category of tools is most likely to deliver the yield benefit I need?" For example, in a world of uncontrollable manufacturing variability, it is more likely that new DFM/DFY technology can have stronger impact with respect to systematic variation mechanisms - which are of more recent concern - than truly random variation mechanisms. Tools that predict and compensate for systematic variations, followed by tools that explicitly reduce the inherent sensitivity of the chip to those variations, will be deployed before tools that address random variations.

Another axis of the DFM/DFY taxonomy is whether the tool improves parametric yield versus functional (i.e., defect) yield. Functional yield has less opportunity for quantum leaps, since process engineers have known for decades how to perform cycles of functional yield learning (process changes, design rule changes, etc.). It is risky to be too aggressive with defect yield improvements: what enhances defect yield today may well hurt it tomorrow. At the same time, purported parametric yield enhancements - that is, with respect to Iddq and Fmax criteria, or "what the designer cares about" - also demand careful evaluation. While parametric yield improvement is always attractive, a number of practicalities must be comprehended. For example, if a tool leverages proprietary process models from the foundry, does the rest of the design flow use the same models in a consistent manner? Or, if a tool puts the "virtual fab" onto the designer's desktop, is this necessarily a good thing? The CTO must seek a clean separation of concerns between design and manufacturing: designers do not want to have to learn about low-k1 lithography or non-Prestonian CMP models, and in general it is risky to assume that new skill sets will grow overnight within the design and CAD teams.

Yet another axis is whether the DFM/DFY tool performs optimization versus analysis. Analysis can identify problems, but may not be useful without a proven methodology to fix them. Even then, the analysis will not be useful if problems are too numerous and design iterations become non-convergent. Ultimately, DFM/DFY must make the chip better, i.e., perform optimization to complete the circle from analysis. The CTO should be on the lookout for scalable solvers for truly difficult optimizations, as well as unique and substantial QOR improvements that cannot be achieved in any other way, and that justify adoption risks.

Finding the right technologies from among the plethora of DFM/DFY offerings can yield significant rewards. A fabless semiconductor CTO should seek to identify the truly groundbreaking technologies that can have the most impact, and whose deployment requirements can be met in the appropriate time frame at a reasonable cost. With these simple filters, it becomes straightforward to identify the DFM/DFY technologies that are worth a closer look.

Dr. Andrew Kahng is Chairman and CTO at Blaze DFM. He has been an advisor to numerous companies and was chair of the ITRS international technical working group for design. Dr. Kahng has an A.B. in from Harvard College and M.S. and Ph.D. from UCSD.