:: Products To Watch

LogicVision and Mentor Graphics Partner to Deliver Superior Transition Delay Fault Coverage with ScanBurst™

A major issue faced by SoC design teams migrating to the 90nm and 65nm process nodes is the precipitous increase in yield fall out caused by performance and delay faults. At 90nm, it is estimated that 30% of yield fall out is due to performance and signal integrity faults.

As a result, accurate and cost effective at-speed manufacturing test and characterization has become more critical than ever for achieving high quality silicon. Traditional at-speed test approaches that rely on "double capture" techniques have proven inaccurate in identifying performance issues, resulting in potential test escapes or overly optimistic device performance characterization.

LogicVision's BurstMode Timing™ architecture offers an excellent way to address these issues. A key component of the company's ETLogic™ logic BIST offering. this at-speed scan timing infrastructure is now available within a standalone product, ScanBurst, to work with traditionall Scan/ ATPG methodology.

LogicVision has teamed up with Mentor Graphics to make this new product, called ScanBurst, fully compatible and seamless with industry-leading FastScan™ and TestKompress™ ATPG products.

ScanBurst provides comprehensive design automation for generating and integrating the on-chip distributed clock and scan control logic that enables the application of at-speed scan patterns using a single at-speed capture cycle.

The traditional "double-capture" technique has also suffered from what is referred to as "clock stretching."

This phenomenon is caused by the instantaneous drain on power rails during the launch and capture cycles. This results in an increase in the clock period -- and typically, in an optimistic performance rating of the device, or reduced delay fault detection.

The BurstMode technology avoids this situation by providing for programmable ramping of the at-speed clock activity before each test capture. This ensures that the power rails have recovered from the initial instantaneous voltage drop (no clock stretching) and true functional performance parameters are tested.

Another key benefit that ScanBurst brings to ATPG based testing is the ability to easily and efficiently apply scan patterns in a hierarchical fashion.

LogicVision's patented core isolation logic and control technology greatly simplifies and optimizes the generation and application of scan patterns to individual cores. This provides several significant benefits including reduced test generation time, robust pattern generation and reduced test pattern data. Applying at-speed scan patterns to only an arbitrary subset of a design's cores allows trading off test time with average power levels during test. This capability is key in dealing with the growing number of low power designs.

ScanBurst and the FastScan and TestKompress products are available separately from their respective companies.

LogicVision Introduces Yield Insight™

The shift to nanometer-scale designs has challenged semiconductor vendors with increasing variability in the manufacturing processes and growing design-process interactions that lead to an increasing number of yield, performance and quality issues. The result is longer yield ramp-up times, unexpected yield excursions during production, and quality issues in the end product that result in more field returns. To understand the causes of yield loss and to obtain actionable information that can be fed back for yield improvement, a structured yield learning approach is needed.

Traditional yield learning approaches tend to be ad hoc and suffer from data availability issues. They utilize error-prone manual analysis techniques. Collaboration among the various team members is largely through word-of-mouth. In addition, these approaches mostly focus on pins-out analysis, i.e., they look only at the externally visible behavior and parameters.

To ensure the fastest yield ramps possible, an effective yield learning process must be automated, collaborative, repeatable and based on extensive data, including sub-die level information that can help explain how individual design components interact with the manufacturing process to affect product yields.

LogicVision's Yield Insight product has been specifically created to comprehend the large volumes of available semiconductor manufacturing and test data, especially design component level failure and performance information from LogicVision's Embedded Test products. Yield Insight will help analyze this sub-die data, captured across multiple die, wafers and lots, to provide actionable information to the design, fab and test functions to help remedy yield issues.

Yield Insight will initially support sub-die level data from LogicVision's embedded test products. It will also support data from various stages of semiconductor manufacturing and test (including e-Test, Sort and Final Test, etc.). Users can analyze yield issues down to the design component level, and for example, identify design blocks that are failing the most often and the factors that these failures are correlated to, or for example, determine how yields would be affected by changing memory redundancy.

Yield Insight provides powerful graphical analysis and scripting capabilities that allow users to automate and standardize their yield analysis processes. Users can create data-mining rules that sift through the test and yield data to automatically identify potential issues. Yield Insight offers a structured and highly effective yield learning platform. Semiconductor vendors, IDM and fabless alike, will benefit from Yield Insight during the entire semiconductor manufacturing and test cycle, starting from silicon bring-up and characterization, and extending into the yield ramp and volume manufacturing stages.

By accelerating yield ramps and helping quickly remedy yield issues during volume manufacturing, Yield Insight can help improve time-to-volumes and increase product margins and reliability.