:: In the Media
The latest coverage on test, yield, DFM, and DFY.
EE Times, 10/2/06
Standard for 'Open DFM' takes initial steps
By Richard Goering
Requirements for a standard, open design-for-manufacturability model began to be hashed out last week by representatives of foundry, fabless and EDA providers. Participants of the Open DFM Model Workshop explored issues ranging from DFM flows to encryption and identified possible next steps.
Test & Measurement World, 10/1/2006
Preview: International Test Conference
By Rick Nelson, Chief Editor
Test engineers can expect to confront RF, memory, and compression-based-scan test challenges; perform timing measurements; deal with manufacturability and yield issues; and contend with soft errors. That observation is based on the line-up of new full-day tutorials planned for the International Test Conference, which will be held during the week of October 22 in Santa Clara , CA .
EE Times, 9/29/06
Meaning and value of DFM questioned
By Richard Goering
Today's design-for-manufacturability technology is too complex, speakers told the Bacus Photomask Technology Symposium here last week. Instead, they suggested the use of standardized layout elements, library cells or an "integrated" DFM methodology
EE Times, 7/24/06
Designing without a net: Restricted design rules challenge DFM's role
By Richard Goering and Dylan McGrath
This week's Design Automation Conference will make it clear that the EDA industry is counting on design-for-manufacturability (DFM) for a much-needed boost. But the restricted design rules (RDRs) that are quietly emerging for 45-nanometer and smaller geometries may reduce the need for some DFM tools and techniques, some observers say.
EE Times, 5/22/06
Design-for-yield tops designers' wish lists
By Richard Goering
Chip designers today place a high value on design-for-yield (DFY) techniques and capabilities,according to survey data collected at recent Synopsys Inc. user seminars and made available to EE Times. In the survey, 68 percent of some 409 respondents said yield has become a key consideration in their selection of EDA tools.
