:: Big Testers, BIST and Better Yields

Jim Healy's career has followed the major innovations in IC test

The smaller-faster-cheaper trend that so aptly describes the semiconductor industry has created a very different mantra for ATE gear: Faster, yes, but bigger and considerably more expensive.

As the ATE industry struggles to keep pace with what it must consider the curse of Moore 's Law, more and more IC industry veterans are seeing a tipping point on the near horizon: A time when the mainstream test methodology moves from ATE-implemented externally driven test to internally driven test in which the testing actually takes place on the die.

LogicVision CEO Jim Healy has already seen the future -- more than once.

Healy has pretty much been on the leading edge of IC test since the 1970s. Having worked for many of the biggest names in IC test since it began with Fairchild Test Systems, he is adept at reading the writing on the wall. Executive-level stints at ASAT USA , Credence, Genus and Spirox USA testify to his ability to catch the biggest technology waves and ride them to the beach.

So when LogicVision offered Healy the job of CEO in December 2003, he jumped at the opportunity. He firmly believes ATE augmented by Built-In-Self-Test provides the required, flexibility, capability, and investment return needed to economically test 90nm and beyond SoC technologies.

Beyond ATE

He believes that ATE that drives automatic test pattern generators (ATPG) still has a place in testing SoCs-- and can still be a very useful test methodology-- but in these days of larger, exceedingly fast and complex chips he is well aware of its shortcomings: ATE does not test at speed; it targets specific faults; and it is always one generation behind each IC generation.

Healy, who has a penchant for the sea judging from the nautical art on the walls of his office, likes being at the helm of the BIST flagship. Because BIST is implemented internally -- eyes on the die, so to speak -- it runs at the same speed as the chip's clock, tests pseudo-randomly to catch corner cases better, and is in lockstep with IC process nodes because it is part of the chip itself.

LogicVision's ET Create tools are unrivalled in their ability to automatically design built-in test structures. It is widely considered the best third-party BIST tool and works with the design flows of Cadence Design Systems, Synopsys and Magma Design Automation.

Meanwhile, ATE test strategies are changing. While it is widely used to test analog mixed-signal ICs, it is never used for embedded memory, and its utilization for complex logic test is in large part determined by the IC company's test strategy.

BIST and ATE can be synergistic. ATE combined with pseudorandom BIST can find virtually all the faults on an IC. In fact, LogicVision's ET Access interfaces internal test structures with external testers to identify and analyze device failures.

Beyond BIST

As he metamorphosed from a "Big Tester" CEO to a BIST CEO, Healy recognized pretty early that putting specialized structures on the die and analyzing device failures can -- and should -- go beyond the traditional bounds of DFT, which gets you as far as sorting the chips that meet specs from those that don't.

Particularly at the 90- and 65-nm nodes, binning chips as fail/pass is not the surest road to profitability for a specific design. Time-to-ramp to production level yields has become increasingly crucial to the bottom line. Yet chips were failing in alarmingly greater numbers in these advanced process nodes than had been the case even at the 130-nm node.

The reason: Classic impurity-related defects that created failed ICs are being overshadowed by performance-related problems that result from interactions between the design and the process. And since the problems are performance related, in-field failures and returns also became a bigger problem.

Performance-related problems are almost always specific to the design and cannot be adequately addressed by improving process technology or by simply creating design rules that address yield.

Instead, adaptive solutions that measure and analyze parametric data and offer specific design and debug options must be utilized to adequately address performance-based yield problems. Lots and lots of data must be collected from inside the chip to do this. And guess what? Nobody is in a better position to do this than a BIST company.

Yield has always been a key parameter affecting the profitability of a semiconductor product. But until 90nm, yield improvement was typically tied to making adjustments inside the fab. Starting at the 90nm node, design-process interaction became a major issue and yield improvement had to be looked at from a much broader perspective.

At just about the time Healy arrived at LogicVision, the writing was on the wall -- new solutions had to be created to address the emerging yield issue, both for the design stage and for the post-silicon stage . A number of smaller companies were already focusing on the analysis of post-silicon test and fab data to help improve yields. One with the most advanced technology was SiVerion, an Arizona-based provider of automated yield analysis solutions.

LogicVision acquired SiVerion late in 2004 and stole the march on its competitors by positioning itself as the first yield learning company.

Yield learning is a post-silicon technology, says Healy. As you build more and more parts you learn more and more about why they are failing and how their performance is being affected by design and fab decisions. It becomes possible to provide advice to both process engineers and design engineers to improve yields and shorten the design-to-yield ramp.

Data from "eyes in the die" is exactly what is needed for yield learning; and that expertise is precisely what a BIST leader like LogicVision brings to the party. As one might easily imagine, collecting gigabytes of data about a chip's operating characteristics from test structures strategically positioned on the chip is not a walk in the park.

Once the data collection is accomplished, the second task is to analyze it to identify yield limiters and feed back actionable information to the design, fab and test functions to improve yields. LogicVision's SiVision product, which comes from the SiVerion acquisition, was designed to do exactly that. Companies that adopt it are reporting shorter yield-ramp times. The synergies between BIST and Yield Learning turn out to be even greater than the ATE-BIST synergies.

Industry wide adoption tends to be a slow process in the IC industry and yield solutions find themselves today getting ready to leap the chasm between earlier adopters and mainstream implementation.

According to Healy, the toughest problem facing the DFY movement today is not technology. That is starting to fall in place, despite the fact that DFY startup companies are popping up like mushrooms to claim a yield focus these days.

Because the most effective yield improvement methodologies are implemented in the design phase using BIST, IC designers have to also buy into the shift. Most people see the world through the porthole of their own job and most designers are no different. They've not implemented BIST in numbers that will really drive the market, he says, because from their perspective these processes don't provide direct benefit within the design phase and it does require additional work.

Leadership in significant shifts in design practice have to be initiated a higher level, he says, an in those cases management may have to mandate BIST for all designs for the benefits of DFY to be realized.

Since Healy has spent most of his professional life at the leading edge of technology, the reluctance of designers to change is no big surprise. It take effort and dedication to push the stone up the hill, he says, and its only after you've got it to the top that people call you a visionary.