:: Executive Briefings

ARM's view: Why design for low die cost and design for yield are in conflict

Keith Clarke, Vice President of Technical Marketing at ARM, looks at the yield issues of 90nm and 65nm process technologies for both system IP and physical IP.

Now that 90nm process technology is moving to high volume production, the industry is much wiser to the interaction between the design process and manufacturing.

At one time, Design for Yield (DFY) was implicit: "follow our manufacturing design rules and we'll make it yield." Unfortunately, at advanced process nodes a layout that has been optimized for area and follows all the rules but ignores the dozens of recommended rules may yield very poorly. As a result, design for low die cost is now in conflict with DFY.

Design for Manufacture (DFM) and DFY tools are increasingly being integrated into the chip design flow, and providers of intellectual property (IP) blocks and cell libraries can add significant value by helping optimize the design for higher yields.

ARM has to deal with the move to high volume 90nm production from two perspectives:

• The original business of system IP with synthesisable or 'soft' microprocessor cores
• The physical IP business acquired through Artisan that provides libraries and hard IP cores to designers and foundries.

Both perspectives require significant liaison with the EDA vendors and the foundries but in differing proportions.

Synthesizable cores

The major issue for the system IP side of the business is RAM defects, both soft and hard, as the smaller devices are more susceptible to this. However, the smaller geometries also make more gates available to solve the problem, so cores such as the ARM1156T2-S support error correction detection to compensate. This is particularly important in high reliability applications such as system-on-a-chip designs for automotive.

The cores also include built in self test (BIST) algorithms for the memory structures to improve manufacturing test effectiveness, and ARM is also designing RAM structures with redundant rows to help compensate for any manufacturing issues

Of course the key to minimizing cost is getting the balance between smallest area and highest yield, but an IP provider can only do so much.

What is required is a reference methodology to be developed with the EDA vendors - particularly Magma Design Automation, Synopsys and Cadence Design Systems - to provide a flow from RTL to GDSII that takes into account the details of the synthesis and analysis tools and the design rules of the target foundries.

These design flows are increasingly including cross talk analysis tools that change the layout to reduce noise and signal integrity problems, particularly by moving tracks further apart and adding 'jags' so that two long lines do not resonate together. This is vitally important as 90nm and 65nm processes drive higher clock speeds and there are more radio frequency issues with the layout.

Physical IP

On the physical IP side of the business, the main danger is optimizing a cell for yield such that it becomes too large. It is vitally important to balance the size of elements such as memory cells with the yield.

So ARM is working with the EDA vendors to use yield parameters from the major foundries in the cell library alongside the size, power and speed data to give the design tools the ability to optimize for yield alongside the other factors. However, this process is only just beginning as 90nm yield data becomes available in quantities that are statistically significant.

There is also a key feedback loop from statistical analysis of manufacturing defects back to the layout s well as with mask making. For example Optical Proximity Correction (OPC) techniques will introduce extra features on masks to compensate for certain layout structures in the current 90nm designs, and these need to be considered in the yield optimization.

Life at 65nm

65nm designs are only now going into initial production, and it is too early to tell what factors will truly affect the yield for these processes. The smaller dimensions mean that even transistors with the same dimensions vary considerably on the same design, and this variation means SPICE models with worst case and best case figures are meaningless. Instead EDA vendors are looking at statistical techniques such as Monte Carlo analysis to determine how the transistors vary and design and simulate with that data.

A lot of work has been done on yield at 90nm, and that expertise is now being integrated into the system and physical IP used by designers as designs move into high volume production. 65nm designs will follow the same process in the next 18 to 24 months.

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