:: Strategically Speaking

Design for Yield: A Category All its Own

Gartner Dataquest recently revised its well-known EDA Landscape to create a new category, "Design for Yield + Modeling." The Yield Learning Report talked with Gartner Dataquest Principal Research Analysts Nancy Wu and Laurie Balch for more insight into this change.

YLR: We've seen considerable growth in companies promising to help designers climb the yield curve faster. Is this a single market or can it be segmented? How are the companies doing as a group?

Nancy Wu: In the EDA realm, the "yield-related tools and technologies" are those that address systematic yield losses during process variation. Parametric yield is the problem they are trying to address from various techniques, such as OPC simulation, critical area analysis, lithography rule checkers and layout optimizer. Some of the work is done by IC CAD engineers, and some by process engineers.

However, there has not been much revenue in the DFM/DFY area in the past few years because the tools/companies were new to the market.

Only RET has good potential to continuously growing, with a 5-year CAGR of about 11% until 2009. RET was growing 90% in 2003, because it was a turning point when the power users were all stepping in the 65nm design, where RET is a must; and mainstream users were all shifted to 90nm, when RET is necessary if you want 95% yield.

Both 65nm and 90nm requires heavy OPC and PSM to get the design right on the mask or wafer. The growth rate declined in 2004 to 6%, when it was saturated in the market so the growth was slowing down.

YLR: With that in mind, why are so many companies jumping on the yield bandwagon?

NW: The brief answer is ROI. At 65 nm and below, the yield on a production wafer will be low enough and leave design or system houses with no/low profit on a table. It's the right time to look for ways to improve yield in both design and manufacturing.

Yield problems are more easily solved by the IDMs because they have the advantage of being able to connect both sides: Design and process/manufacturing.

For fabless companies, the need is for someone who understands the process and is capable of communicating the specific problems in the way the fables companies understand, and vice versa.

So there is a market for those who are able to bridge the two sides together.

YLR: With so many new companies hoping to be the bridge between design and manufacturing, what characteristics will determine the winners?

NW: I'd like to say that good technology is the key, but we've seen many companies with good technologies fail in the past.

There are lots of reasons for a company to exit the market. To be success especially in the DFM space, a company needs to have good technologies, be well funded, and ally with foundries or mask shops to prove the technology.

In terms of technology, I can't give a specific recipe that will lead to success in DFM. Most DFM companies have their own take on how to tackle the DFM problems. Lots of them are really interesting.

YLR: Why did Gartner Dataquest choose to make Design for Yield + Modeling is own category? How does it fit in with CAD, CAM , and test?

NW: At this point, yield can be addressed early enough in place and route, or later in OPC/PSM. It came originally from the IC CAM realm but it slso fits well in the IC CAD design flow.

So far, we haven't seen much that would definitively tell us it can move up beyond IC CAD. Going forward, however, yield will certainly be an important factor for IC CAD tools development.

We can expect to see the retooling in the CAD tools which will drive the growth in EDA.

In physical design, yield can be addressed by DFT, place and route, physical verification, libraries, and DFM (TCAD, RET and others).

Once the concept of yield awareness or yield enhancement is embedded in the IC CAD tools, there may not be a single category for yield. But right now, we're keeping it separate from IC CAD and create its own category which is "Design for Yield + Modeling".

Gartner Dataquest's Laurie Balch answered the final questions.

YLR: Where does test fit into the equation? Can it be linked to yield improvement?

LB: The relationship between test and yield has been basically that once a part fails during test, it generally is then discarded and therefore brings down the yield numbers.

If there were a better way to test early on so that test failures could be tracked back to the design to better understand why failures occur, then the chips could be redesigned to pass the test process, which means higher yields.

This is something that has been discussed for some time in the industry but few tools exist to really close this feedback loop between design and test.  

Part of the problem is that test engineers write and interpret the test programs, while design engineers do the up-front work.  Having two different groups of engineers involved is itself a roadblock.  Also, test programs are written to operate on specific testers which don't all necessarily communicate smoothly with the design tools.  

So getting test data into the hands of the design team in a useable, understandable format that ties into the design environment can be challenging at best.

YLR: Does test need to provide more info than pass/fail to help understand and ultimately improve yield?

LB: Ideally, test data would be fed back to design engineers with not just pass/fail data but also detailed information about where the failure occurred on the chip and at what step in the test sequence.  

Armed with that knowledge, design engineers could better analyze where and why problems were happening and fix the design to avoid the failures.  

Obviously, it would be best to provide this data early on before volume production but presumably you could incorporate design fixes even in later updates to the chip.

For more information on Gartner Dataquest, visit: http://www.gartner.com/