:: Executive Briefing: The Process Intelligence Gap

By: Robert P. Smith, CEO and Chairman, Stratosphere Solutions, Inc.

As the semiconductor industry shifts its core manufacturing process technologies toward the 90nm, 65nm, and 45nm nodes, it must contend with the effects of parametric variability on both yield and performance. In the past, these effects were small enough that they could be ignored - but this no longer the case. This also means that for the first time, chip designers must be conscious of the impact of parametric variability on not only performance but parametric yield of their designs.

Where and how will design engineers get the information they need to improve yield and performance in the presence of variability? Foundries collect data but it is mostly expressed in the language of process development engineers - metrology and process data (for example, defectivity data) - and that is of little help to designers.

Designers are interested in and understand electrical parameters such as threshold voltage, leakage current, drive current and the like - and shouldn't need to become experts in interpreting complex process-related data. Compounding the problem is the fact that the foundries themselves find it uneconomical to collect all of the data that chip designers really need to improve yield and performance under the presence of process variations.

This is just one aspect of what we refer to as the "process intelligence gap."

Inadequate data

Just as important is the fact that the quantity and resolution of data that is readily available at the fabs is insufficient for process engineers to quickly ramp process yield for a new process.

The challenge facing the process development engineer is that the silicon area required for comprehensive design-aware process characterization using traditional techniques is becoming prohibitively large. This is due to the large numbers of high-resolution (analog measurement) test structures required to adequately analyze and model parametric variability. In the conventional approach, each high-resolution test structure is surrounded by a dedicated set of I/O pads. The result is that the area is dominated by I/O pads which ultimately limit the number of test structures that can be economically placed on the reticle.

This makes life tough for process development engineers and even tougher for design engineers. For example, leading-edge graphics and wireless communications companies build proprietary design topologies that give their chips competitive advantage. They are unlikely to want to risk exposure of this IP. Fabs can't possibly predict all of the possible topologies contained within a design. The fab therefore resorts to the creation and use of design rules as a way to manage and contain manufacturability and yield issues.

Unfortunately, this is causing the number of design rules to explode. In fact, many rules are not really rules but are often referred to as "fuzzy" rules (which are really just guidelines and subject to individual interpretation). The explosion in the number of rules and the existence of fuzzy rules have led to designers adopting guardbanding as a defense. This tends to be self-defeating because they typically force the designer to give up both silicon area and performance which are often the very reasons that designers choose to move to advanced process nodes in the first place.

Bridging the gap

Traditional methods of collecting design-aware process data with discrete test structures are not sufficient to support the new generation of 90nm and below process nodes. New, dense, IP-based high-resolution test vehicle technologies are required. These test vehicles will allow fabs to generate an order of magnitude more high resolution analog data using the same area on the test reticle. In fact, the volume of data that can be collected using this approach supports characterization of within-die variability for the first time. The IP is distributed to the fab in GDSII format along with applicable test programs and analysis methods. Flexibility in the IP platform makes it easy for the fab to add their own proprietary test structures to the platform.

What about DFM? Shouldn't DFM be able to help designers comprehend and manage yield?

DFM tools typically build complex mathematical models to predict the behavior of a specific process step such as lithography, CMP, etch, etc. DFM tools are extremely useful for either preparing or verifying a design for manufacturability. However, because they are deterministic and based on mathematical models, they cannot be used to predict yield. Yield is ultimately driven by a complex function of many interacting process steps and physical effects. The IP-based approach, on the other hand, collects high-resolution empirical data from the silicon that can be used to create statistical models to predict yield.

The data can provide a statistical characterization of a device's performance, a process window characterization of a device type, and a large set of design topologies. Design engineers can use this information to extract additional "process intelligence" expressed in the electrical characteristics important to them.

Once a design is in production, a variant of this same silicon IP can be embedded in the scribe lines to allow the fab or fabless company to monitor parametric variability without sacrificing precious silicon area. This allows fabs and fabless semiconductor companies to compare and monitor in-production variability data values to the data obtained during process yield ramp.

Next step

Once the process engineers have a vehicle to collect the mountains of data needed to analyze parametric variability and how it impacts yield, there is still the question of making the data truly accessible to design teams.

Fabs are rightfully reluctant to share process information with any but their most favored customers. As previously noted, however, designers are interested in electrical metrics and not process data. To get around the intellectual property protection issue, the industry needs a modeling platform that separates electrical data from process data. Such a model would allow the fabs to provide their design customers with critical electrical metrics without needing to divulge the underlying process data. Fabs will be much less likely to view the release of information in this form as a competitive disadvantage.

Industry implications

The semiconductor industry is at the cusp of a major transition as it migrates to sub- 90nm processes. Parametric variability, which could be previously ignored, must now be considered. Fabs and foundries have a vested economic interest to move their customers to these new processes and begin to recoup their ROI.

However, designers will be reluctant to move if the believe that they must give up many of the perceived benefits of density and performance due to overly-aggressive design rules and guardbanding.

The industry needs better and more comprehensive ways to calibrate its own processes and better ways to communicate parametric variability data to its customers in a format that they can interpret and use. Designers need to be able to understand how their designs will perform in the face of variability in order to take advantage of the area and performance benefits promised by the newest semiconductor processes being introduced.

Robert (Bob) Smith is the CEO and Chairman of Stratosphere Solutions. Stratosphere Solutions Inc. provides innovative process characterization tools to semiconductor manufacturers.  Its StratoPro product delivers a unique combination of silicon-proven intellectual property (IP) and applications that enables manufacturers to accurately characterize process variations for sub-100 nanometer processes.  Founded in 2004 by semiconductor manufacturing and electronic design automation (EDA) experts, its customer base includes leading worldwide semiconductor manufacturers. 
Corporate headquarters are located at:  830 Stewart Drive, Suite B10 , Sunnyvale , Calif. 94085.  Telephone:  (408) 701-1418.  Facsimile:  Facsimile:  (408) 730-5889. 
Email:  info@stratosol.com.  Website:  http://www.stratosol.com.