:: Strategically Speaking

Yield Learning: Why we are at a tipping point

By Jim Healy, President and CEO
LogicVision, Inc., San Jose, CA

Yield Learning is a new name for an activity that’s about as old as the IC industry itself:

Maximize ROI by optimizing a design’s yield. For the most profitable companies, optimization means more than simply reducing the number of defects and shipping as many functioning devices as possible. Optimization is hitting the right combination of chip performance, time-to-market, and financial goals.

So why a new name?

While yield has always been critically important, for the past half century we could pretty safely ignore the learning, which involves a detailed understanding of what’s really happening inside the chip.

Yield used to be tightly coupled with defects. It was a process problem. After the process bugs were worked out, it didn’t impact ROI that much, particularly in light of time-to-market pressures. At the 0.25µm node, however, we started to see a significant number of chip failures that could not be traced back to silicon defects.

The new class of problems was related to lithography and chip performance. At the 90nm node, there is no doubt that failures related to performance are dominating the yield management equation.

For the past decade, a growing number of technical papers delivered at ITC, DAC and other industry conferences have been warning us about this new reality.

The new reality is upon us. Most failures – including field returns – for designs fabricated at the leading-edge process nodes can be traced to performance issues created by design and process interactions. These interactions are related to speed faults, interconnect parasitics, and leakage-sensitive factors. The faults are typically difficult to model.

Tipping point

There is a huge power design problem that results from chips burning up in the field. Field returns are escalating as a result.
-- The Chip Insider, Dan Hutcheson, VLSI Research, May 2005

Although many bad devices can be caught in manufacturing at probe or final test, many others are being shipped because of insufficient test coverage. Some burn out in the field and for many others – surprisingly to most companies – failure analysis of the field returns results in “no problem found” (NPF).

Many new customers of LogicVison and its technology partners say that the sudden appearance of a raft of NPF returns almost always means that defect coverage was too low. Compounding their yield problems is the fact that devices are seldom tested under the functional conditions in the end application. Not infrequently, system design margins are too narrow as well.

There are many technology touch points where yield learning can reap big benefits for designers, test engineers and product engineers – not to mention CTOs, CFOs and CEOs. A good example is catching the hard-to-model problems mentioned earlier.

The best way to catch them is at-speed high transition fault coverage combined with a high N-detects, which is a means of measuring how many times each modeled fault is detected under varying conditions. It’s an excellent way to measure defect coverage.

But this kind of testing is already pushing ATPG – including ATPG compression – beyond its practical limits. Why? Because ATPG pattern counts grow rapidly with increased N-detects. Our view is that embedded test is the optimal solution because you really need to know what’s going on inside the chip.

At-speed pseudoramdom BIST, with its inherently high N-detect, typically results in defects per million dropping precipitously.

ATPG is a technology that will probably be around for a long time to come. But companies that rely on it exclusively have to make a difficult tradeoff between poor fault coverage and prohibitive test costs. This tradeoff disappears with BIST.

Yield learning

The recognition of the importance of yield learning is growing rapidly as more and more companies transition their designs to the 90nm node. There is still much to learn – much to understand. All the clichés really do apply: paradigm shift, tipping point, new reality – they all demand a new perspective

That’s why LogicVision and its technology partners conceived The Yield Leaning Report: To promote a better understanding of the relationship between design, test, and manufacturability.

According to the research firm IBS Corp., the probability of a design re-spin at 90nm is over 30% but with many SoC devices it can be over 90%. The failure rate is high because we don’t know enough about what’s going on inside the chip. Yield learning is a discipline that will help us acquire that critical knowledge. We hope you join us on this voyage of discovery by subscribing.

To subscribe to the Yield Learning Report, click the link below:

http://www.yieldlearning.com/subscribe