:: Executive Briefings

Five Things Every CTO Should Know About Yield

1. Defects are not the primary cause of yield problems.

Of the three factors determining yields, defects such as submicron impurities in the silicon have accounted for less than half of all problems since the 0.25µm node (click link below to see graph).

Figure 1. Defects from impurities becoming less important

Solving lithography-based and performance-based yield problems is far more important to CTOs today. Moreover, the trend is clearly toward performance-based problems dominating a CTO’s yield agenda. At the 90 nm node, they will account for about 60% of all failures.

Performance-related problems are highly sensitive to design-process interactions. They are almost always specific to the design cannot be adequately addressed by improving process technology or by simply creating design rules that address yield.

Adaptive solutions that measure and analyze parametric data and offer specific design debug options must be utilized to adequately address performance-based yield problems.

2. If you’ve waited for first silicon, you’ve waited too long.

Every CTO knows exactly how costly design respins are in time and money for his company. The really bad news is that at the 130 nm node, the probability of a design re-spin nearly doubles compared to the 0.18µm node; and at the 90 nm node respins are still another one-third more likely. Unless, of course, design defects are adequately addressed up front. The probability of re-spin at several process nodes is shown below.

Figure 2. The probability of design respins is rising rapidly.

Since a re-spin usually adds between four and eight months to a design, it has an enormous impact on profitability. Clearly, yield enhancement solutions that avoid re-spins or shorten the time needed to revise the design are essential to a CTO’s profitability agenda.

3. True yield depends on more than how many parts you ship.

Although it was once a safe bet to start calculating profitability once dice had been packaged and shipped, it’s a bad bet at the 130nm and 90nm nodes.

Performance-based problems are sensitive to operating environments, so unanticipated rates of field returns for deep submicron designs are common. This can have a devastating effect on profitability. While yield management can correctly be considered a “first silicon” effort, the effort of applying the highest possible level of design debugging techniques for yield is multiplied by reducing field returns.

4. Yield learning is the best basis of yield management.

A relatively new concept, yield learning offers a comprehensive solution. It is the process of iteratively identifying and addressing the problems limiting yield, which include defects, functional & performance issues, and parametric issues. Yield learning is applied to the two main requirements for yield management: (1) to optimize the design performance debug loop (see figure below); and, (2) to optimize the parametric yield debug loop. Yield learning tools to accomplish these goals are reaching a high level of maturity and effectiveness.

Figure 3. Yield Learning optimizes the design performance debug loop.

5. Months of manual tweaking? It’s an outdated methodology.

Many CTOs acknowledge the value of aggressive yield management but still demand a definitive answer on the methodology’s cost/benefit analysis. In the past, parametric performance verification, for example, was a manual and time-consuming process. To avoid adding four to five weeks to the design cycle, some CTOs were willing to take the risk of a design re-spin.

The recent availability of tools that optimize and automate parametric performance verification has dramatically changed the cost/benefit analysis. Platforms such a LogicVision’s SiVision, consist of algorithms, rules and best practices that perform evaluation, detection, and root cause identification of performance issues. Instead of taking two or three product engineers for four to five weeks, automation takes one engineer just four to five days.

This executive summary was created by The Yield Learning Report to enhance understanding of the problems posed by yield at the 90nm node and beyond. To read a more detailed discussion of yield issues and their solutions, link to the white paper Advanced Yield Learning on TechOnline.

If you have a question, a comment, or would like to contribute your insights or yield learning experiences to the Report, please visit our Web site at :

http://www.yieldlearning.com