The Yield Learning Report - Connecting design, test and fab

:: Events & Shows

DAC DFM Sessions at a Glance

Date
Time
 Session Topic
6/13
9:00 am
MONDAY TUTORIAL
Statistical Performance Analysis and Optimization of Digital Circuits
SESSION 7 Statistical Timing Analysis
6/14
7.1
 Parameterized Block-Based Statistical Timing Analysis with Non-Gaussian Parameters and Nonlinear Delay Functions
6/14
HOTSoc
 Designing Extendable Cores with Low-Cost Metal Programmable Technology (Magma Design Automation, Inc.; CoWare, Inc.; MIPS Technologies, Inc.; Virage Logic Corp.)
6/14
7.2
 Correlation-Aware Statistical Timing Analysis with Non-Gaussian Delay Distributions
6/14
7.3
 Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model
6/14
7.4
 A General Framework for Accurate Statistical Timing Analysis Considering Correlations
6/14
PANEL: DFM Rules!
SESSION 19: Statistical Optimization and Manufacturability
6/15
19.1
 An Efficient Algorithm for Statistical Minimization of Total Power Under Timing Yield Constraints
6/15
19.2
 Robust Gate Sizing by Geometric Programming
6/15
19.3
 Circuit Optimization Using Statistical Static Timing Analysis
6/15
19.4
 An Optimal Jumper Insertion Algorithm for Antenna Effect Avoidance/Fixing
SESSION 23: Design Methods for Manufacturability Enhancements
6/15
23.1
 Design Methodology for IC Manufacturability Based on Regular Logic-Bricks
6/15
23.2
 Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
6/15
23.3
 Self-compensating Design for Focus Variation
6/15
23.4
 RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations
SESSION 32: Impact of Process Variations on Power
6/15
32.1
 Full-Chip Analysis of Leakage Power Under Process Variations, Including Spatial Correlations
6/15
32.2
 Variations-Aware Low-Power Design with Voltage Scaling
6/15
33.3
 Accurate and Efficient Parametric Yield Estimation Considering Correlated Variations in Leakage Power and Performance
6/15
33.4
 Leakage Minimization of Nano-scale Circuits in the Presence of Systematic and Random Variations
SESSION 40: Circuit Performance Under Parameter Variation
6/16
40.1
 Statistical Static Timing Analysis: How Simple Can We Get?
6/16
40.2
 Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach
6/16
40.3
 Power Grid Simulation Via Efficient Sampling-Based Sensitivity Analysis and Hierarchical Symbolic Relaxation
SESSION 46: DFM and Variability: Theory and Practice
6/16
46.1
 BEOL Variability and Impact on RC Extraction
6/16
46.2
 An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization
6/16
46.3
 Variation-Tolerant Circuits: Circuit Solutions and Techniques
6/16
46.4
 On the Need for Statistical Timing Analysis
6/16
46.5
 CAD Tools for Variation Tolerance
6/16
46.6
 Are There Economic Benefits in DFM?
FRIDAY TUTORIAL
6/17
Design for Manufacturing at 65 nm and Below