Yield Learning

| IN THIS ISSUE |

Executive Briefing: Correct by construction: Yield enhancement for the 21st century.

Strategically Speaking: How process complexity will change the IC industry's business models.

Tech Paper: Lithography-aware design enables 'extreme' RET.

Design for Manufacturing: DFM for advanced technology nodes: Fabless view.

Test Topics: When probing goes in the chip.

White Paper: Design for Test Fundamentals

LogicVision's SiVision 4.0 accelerates time-to-volumes without comprising quality.

TI picks BlastFusion® for its low power 65-nm designs

15 Minutes of Fame

:: Technical Papers

Lithography-aware design enables 'extreme' RET

Traditional methods for ensuring manufacturability of IC designs are largely ineffective at advanced nanometer nodes.

But with the evolution of complementary design-aware lithography and lithography-aware design, semiconductor manufacturers will be able to take full advantage of advanced manufacturing technologies in the development of next-generation devices.

In this Tech Paper first published in EE Times, Cadence Design Systems' Wolf Staud and Bob Nabor discuss new and more effective ways to link lithography and design.

Lithography-aware design enables 'extreme' RET