:: Strategically Speaking

How process complexity will change the IC industry's business models

An exclusive Yield Learning Report Interview with Bob Johnson, Research Vice President, Gartner Dataquest

YLR: We hear a lot about advanced process nodes giving designers and manufacturing engineers fits, about initial yields in single digit percentages and so forth. What is the underlying problem in the fab?

Bob Johnson: Each manufacturing step has tolerances and no step will work exactly as it supposed to the first time out. If one process step drifts a little bit toward one side of the tolerance range, it may requires adjustments in other steps to compensate. However, if there is a basic problem with a mask layout, there is a limit to how much correction can actually be accomplished at the fab and still make working devices.

YLR: How does the industry address that problem?

BJ: At advanced process nodes, complex process models must be built into the design phase further upstream. Tool variations have to be built into a model that help designers avoid using structures that have become pretty much impossible to build because they interact with each other.

YLR: When is this going to hit big time?

BJ: Certainly at the 32-nm node -- with some at 45nm.

YLR: In other words, design has to become more interactive with process.

BJ: Yes, the top IDMs talk a lot about how they're getting their design people working with the fab people. That works fine for the likes of Intel, IBM, TI, the memory companies.

YLR: What about fabless semiconductor companies?

BJ: Well, the question for the foundry is "To whom do open your kimono?" Are they willing to give a company a set of design tools that effectively publicly exposes the details of their process?

In fact, some foundries don't see that as problem. They think they can work through 90 nm and 65 nm with existing design approaches. Or, they can work closely with a trusted company to tweak things back and forth. AMD and Charter is a good example. That's a significant long-term relationship and both are part the IBM technology sharing consortium.

YLR: Not all companies are as big as AMD, Xilinx, nVidia. What's their fate?

BJ: That's a good question. For starters, the foundries would probably want to have a secure process model. That means designers would plug their design into a black box that tells them the design will or won't work. It would also offer advice to tweak specific areas and maybe even what tweaks to make. With that concept, however, you would still have some real IP issues going on.

YLR: But if we were to assume for the time being that secure models would be available, would that be enough?

BJ: There's more to it than that. The black box concept has limitations because there has to have continuous learning about what these systematic defects are.

YLR: Why?

BJ: Some of the defects you find in the advanced processes are unpredictable from node to node. One of the current problems in memory is poly stringers across the trench of the capacitor where the poly stringer literally shorts out the trench.

Different defect mechanisms keep appearing and would require the continuous updating of this model.

YLR: What does continuous updating mean for the designer who is not working for a Xilinx or nVidia?

BJ: It is possible that a designer could have followed all the rules and is ready to hit the tape-out button. All of a sudden, he has a total revision of design rules. Is he going to go back or and redo the entire design or is he going to take his chances? It's not a pleasant set of alternatives. With continuous updating, he would get improved data throughout the design process, minimizing the chance that a complete re-design is necessary at the end of the process

YLR: Are we at a tipping point in terms of business models for IC companies and foundries alike?

BJ: I would not be surprised to see foundries starting to develop the capabilities similar to those we used to call ASIC houses: "Bring us your electrical design (circuit layout) and we'll take it from there."

YLR: What does this mean for the industry? Will there be top-tier fabless companies that can operate at the leading edge and all the rest who lose even more access than they have now to leading edge processes?

BJ: It's an interesting question. To answer it you have to ask yourself what kind of products can take advantage of 45 nm? Clearly, you're looking at full systems-on-chip for the most part.

So you might find that fabless semiconductor Company A has a very nice RF amplifier or an encoder for a cell phone. That's fine, but it just a piece of the SoC that runs the cell phone. So the company has two choices. It can get together with other companies and put together the full system on chip, or, it can sell its design as IP.

Some of the companies that are selling chips today may move to become IP companies like ARM.

YLR: In othe words, another round of consolidation caused by process complexity?

BJ: It can consolidate either with some people going out of business, some people becoming IP providers and some people merging together to have a more comprehensive list of platform offerings.