:: Executive Briefings

Correct by construction: Yield enhancement for the 21st century

By Dan Nenni, Vice president of marketing, Predictions Software Ltd.

Until the CEOs of semiconductor companies make chip designers responsible for achieving economically optimized yields for their designs, the unprecedented yield problems the industry is experiencing at advanced process nodes cannot be solved.

This is a major shift in responsibility. Yield was once the exclusive province of manufacturing. With the shift in responsibility will come an equally important shift in design tool methodology.

As a practical matter, for all but the most advanced companies yield enhancement has not moved much beyond place-and-route in the design flow. The result for many IC companies is an ad hoc approach to yield that is based on trial and error and learning from one's mistakes.

Some yield enhancement companies have made a business doing "chip autopsies" after designs fail to yield beyond single digit percentages. There are a number of EDA tools from smaller firms that claim to put yield enhancement into the hands of designers. We have yet to put them into widespread use as an industry.

Contrary to common opinion, designers are interested in helping solve the yield problem. But they need tools and -- as typically happens -- the major EDA tool vendors have been slow to react. The current crop of "yield aware" solutions they offer falls short of a real solution.

EDA companies must accept the fact that detailed process information has to be available to design engineers at every step of the design flow -- and they must create or integrate tools that use it at every step.

Foundries must accept the fact that they must supply process information (yield models) to their customers even though it is highly sensitive information. The solution is to encrypt the process information within the yield analysis tools.

Trial and error

Learning by trial an error as we have in the past is not an option. To cite just one example: Yield loss in 90nm processes tends to be dominated by short circuits. At 65nm, it tends to be dominated by breaks. The ability to carry even the most rudimentary yield know how from one node to the next is no longer viable.

But getting detailed process data from foundries is not just a problem generated by proprietary or competitive information restrictions. In fact, foundries don't have the complete data either. It is, after all, constantly changing and design dependent.

This has resulted in a "yield aware" approach to IC design that relies on incomplete process data that is applied almost randomly during the design cycle. The best that can be hoped for is expensive mask touch-up services. Can designers design for yield when they don't accurately know what it is? Absolutely not.

Correct by construction Extracting test data from design

The EDA industry has to get past awareness and become "yield driven." This starts with analysis of design building blocks such as standard cells, memories, IP blocks. It also includes analysis right through full-chip implementation. Yield driven means applying factual, verified design and process yield information to the design so it is created with a "correct-by-construction" methodology.

Correct-by-construction requires three things:

• Integrating process defect data into the design cycle to predict and prevent faults from random, parametric, systematic, and user defined defects.
• Identifying the regions of a design that are susceptible to faults by providing efficient critical area analysis.
• Optimizing yield by determining which DFM techniques are best for the targeted process.

If yield analysis tools are to be truly useful for designers, then they must be applied at every level of the design -- they must also be fast.

There are basically three methodologies for critical area analysis: flat, hierarchical, and sampling, or statistical analysis. With the flat methodology, operations are performed on the entire layout. Compute resources and time constrains limit this methodology to layouts of about 5000 transistors.

The hierarchical method can be the most complicated and time consuming because it depends on how the circuit designer used hierarchy in the layout. Sampling as applied by Predictions Software Ltd. is the most efficient method as it can give fast full-chip results in tens of minutes on modern systems.

Conclusion  

Process engineers have been using critical area analysis, yield models, and yield prediction for more than a decade. All three are trusted weapons in the fight for efficient semiconductor manufacturing.   On the design side, with the ability to clearly illustrate the different factors that determine yield, provide detailed analysis, then account for it in all phases of the design cycle, IC designers can focus on correct-by-construction design practices, expedite yield problem resolution, and build the strongest bridge to manufacturing available today.   This new level of communication between design and manufacture will ensure that nanometer technology will be properly realized on silicon.