:: Strategically Speaking

Rules vs. Models: Technology discontinuity at 90nm

An exclusive Yield Learning Report Interview with Alex Alexanian, CEO of Ponte Systems Inc.

Initial yields at the 90nm node are reported to be in the single digits. Why?

One reason is that design teams are still working under the assumption that yield can be adequately addressed by following design rules provided by the fabs. Design Rule Checking (DRC) tools ensure that the design can be manufactured and can function -- that is their primary purpose.

At one time, this was also enough to achieve reasonable initial yields that the fab could improve by tweaking the process. At 90nm, however, this is no longer true -- but the idea is still commonly held.

An important distinction should be made: Rule checking is a Design for Manufacture (DFM) technology. At 90nm and beyond, it is a DFY (Design for Yield) solution.

Why do design rules no longer assure adequate yield?

At 90nm, spacing rules, for example, become conditional. The process cannot be described by a set of rules such as minimum spacing or width. Metal fill rules are not percentages. They are window-based.

DRC provides a binary result: either the design is compliant or it is not. This does not address the reality that sometimes over the range of manufacturing conditions the rule describes the process accurately -- and sometimes it does not.

Design rules have run out of steam as far as yield is concerned. What's the solution?

Modeling the manufacturing process provides a much closer representation of reality.

A model is a generic representation of the chemical process technology. It is constructed by first capturing all the important physical, mechanical and chemical characteristics of each process step.

The model is an abstracted version of this data. It describes how these characteristics exhibit different behaviors depending on design features. Design teams use the model to simulate the design as it would be manufactured in the fab.

The information derived from the simulation can show the design team which parts of the chip are likely to have yield problems. EDA tools that understand how to use this information can be called Design for Yield (DFY) tools.

Modeling the process provides much better predictions of failure probability. This is best shown by a graph.  

There seems to be a wide gulf between design and manufacturing. Is this true?

Design and manufacturing are two entirely different worlds. After verification, designers throw the design "over the wall" to manufacturing. On the other hand, process engineers have always been focused on the wafer, not the design. They want to be sure that the chip is manufacturable with their process. This does not mean that the chip will yield. As we noted earlier, it may yield in the single digit percentages.

Is a yield model a means of communicating between those two worlds?

Yes. Part of our company's name is ponté, which means "bridge" in Italian. We see our technology as bridging the design and manufacturing worlds.

When models are used, is there a two-way exchange of information?

At this time, there is not much the design team can do about changing process that is run in the fab. But if they have detailed information about which parts of the design are susceptible to process defects they can inoculate or immunize the design from the specific types of defects that characterize that specific process.

It seems that most of the burden falls on the designer? What's the fab's role?

Fabs already tweak their recipes for different type of chips. They use different recipes for memory and logic chips, for example. We believe that the recipe can be tweaked for every design to make it yield better.

That is something we want to achieve in the future.

How successful is modeling technology at improving yield?

One of the advantages of DFY tools is that yield is easy to quantify. From a business perspective, EDA products are purchased based on an expected return on investment. DFY tools can be very expensive. They cost in the hundreds of thousands of dollars. But we have found that the return on investment for our customers can be a month or less.  

Why is the ROI so fast?

There are two primary advantages to DFY tools. They increase yield -- and they shorten the design cycle. DFY tools can inform the designer that the design will not yield well and that it should not go to the fab without changes that will enhance yield.

If you go to the fab too soon and the design doesn't yield there's nothing you can do about it but go back and respin the design. The loss in time to market is at least four to six months, which can be a substantial part of a design's revenue over its lifetime.

DFY tools also accelerate time to volume.

Are there tradeoffs involved with DFY tools in terms of chip size or performance?

It is generally thought in the industry that optimizing for yield requires tradeoffs such as the chip becoming larger. But we have not found this to be true. Today's design methodologies leave a lot on the table in terms of yield improvement. We have found that with a model-based approach, yield can be significantly increased without increasing the chip's size.

Thank you.