:: Executive Briefings

Physically-aware DFT adds a new dimension to IC yield learning

By Dwayne Burek
Director of Product Engineering for Test, Magma Design Automation

As the IC industry moves into the realm of 90-nm and 65-nm designs, meeting constraints such as area, timing and power is becoming ever more difficult. One consequence of this trend is very well known: Designers are struggling to maintain predictable schedules.

A less frequently discussed but just as important challenge involves IC test. To be economically successful, an IC must meet at least four criteria. It must be manufacturable, testable, have an acceptable yield ramp, and meet pricing targets.

In the past, the EDA industry has treated the first three criteria as nearly separate entities addressed by separate tools. The industry has practically taken for granted that pricing targets would be achieved as a consequence of meeting the first three criteria.

At advanced process nodes, however, all four criteria are tightly coupled. In particular, an IC may meet manufacturing and yield goals -- it may even be testable -- but the cost of test may be so high that the IC cannot meet pricing targets.

Extracting test data from design

The good news is that although the main purpose of DFT is to provide efficient component test, a comprehensive DFT architecture can also be leveraged for silicon debug, failure diagnosis, and trend analysis for yield management.

While IC test logically follows a chip's fabrication, it is possible to extract critical information about test strategies and metrics during design implementation. Testability is becoming much more design dependent than ever before.

In particular, one important missing capability is having a means of optimizing the parameters that determine the cost of test.

Predictive test means that at almost any time during the design cycle, test metrics can be predicted in much the same way that yields can be predicted by some DFY tools. This gives the design team an opportunity to identify RTL constructs that will cause problems during test and tune specific blocks to meet both yield and test goals.

Traditional solutions that attempt to fix test and yield problems at the GSDII level are severely limited in their range of success because the problem often rests in the design -- and design intent is almost impossible to decipher at the GSDII level.

Achieving predictive test means, however, that DFT tools must be physically aware. They must understand the interdependencies of logic and physical effects and test for the most likely defects. This is only possible if the entire design flow is coupled to a unified data model.

Predictive test

The capabilities of predictive test include:

• Early warning on DFT fault coverage
• Best test strategies at a block level
• Predicting the number of defective devices per million
• Ultimately, the cost of test

Figure 1 shows the concept of physically-aware DFT as compared to current practice.

Figure 1. Evolution to an integrated DFM - DFT solution

In its simplest form, the difference is the addition of a defective-devices-per-million (DDPM) predictor during the design phase and the ability to create physically-aware DFT test vectors optimized to implement an adaptive test strategy.

Adaptive test is highly desired because it allows test engineers to optimize test programs for specific designs, processes (particularly as a the process matures) and libraries. For example, if a particular test pattern is not turning up any defects, it might be a good idea to remove it to shorten the test cycle or to replace it with another test pattern.

The trouble in the past has been that process variation, or, a maturing process, could result in problems where they did not previously exist. Under these new circumstances the abandoned test pattern would find defects.

The lesson learned is that adaptive test can only be implemented when there is a good understanding of the manufacturing process. An integrated DFT solution provides a much better chance of understanding what is going to happen with the design -- and post- design test -- as process changes.

Defect prediction

During design implementation, the DDPM predictor (Figure 1) can provide granular results that will advise the design team about problems in specific blocks. Although the tool can and does forecast the number of defective parts per million, it is much more useful to have reports by block or region.

The design team can access defect predictions on vias, cells, and interconnect stacks.   In this way, improvements can be made or more attention can be spent in specific areas during test.

Predictive DFT can also report fault coverage on a region basis. It can analyze transition delay faults for certain critical paths as provide an overall figure of metric. So instead of one number such as 90% fault coverage for the chip, predictive DFT can advise that there is 85% fault coverage on the paths that have less than 100ps of slack, for example.

Yield Curve Improvements

A comprehensive DFT architecture also allows design teams to trade off between defect control, yield and performance. Depending on the application -- a toy, for example, can tolerate a higher number of defects than a mission-critical automobile system -- the number of defects per million could be "dialed up" in order to increase yield or reduce test time. Being able to understand the dynamics of these tradeoffs early in a design can have a profound effect on outgoing IC quality.

An example of this capability is shown in Figure 2. They yield learning curve of a design benefits from improvement during design that provide a significant positive impact on initial yields during production ramp.

Figure 2. Enhancing the yield learning curve

As previously noted, a predictive DFT architecture that is physically aware can optimize test patterns, tailor test strategies at the block level, and implement adaptive testing. These improvements are manifested by reducing test overkill (declaring good parts as being bad), and test underkill (declaring bad part as being good).

Conclusion

By utilizing the advantages of a unified data model, test strategies can be optimized, test metrics forecast, and tradeoffs made to significantly improve yield learning curves for new IC designs.  

If you have a question, a comment, or would like to contribute your insights or yield learning experiences to the Report, please visit our Web site at:

http://www.yieldlearning.com