:: Strategically Speaking

Mother of all IC Gaps

By Jack Shandle, Editor
The Yield Learning Report

Synopsis: To successfully address yield problems at advanced process nodes, far more cooperation is needed across the traditional functional boundaries of design, test and manufacturing. The author proposes four simple steps to make that happen.

For as long as I can remember, the semiconductor industry has struggled to close gaps. The best known is the design gap - which means that the number of gates that can be integrated on a chip was growing faster than the ability of hardware designers to put them together into circuits.

Design reuse was supposed to close the productivity gap but created a gap of its own - the inability of software engineers working on SoCs to reuse embedded software efficiently. Some people called this the hardware-dependent software gap. About a decade ago, the testability gap arrived - test data was growing faster than the ability to capture and analyze all the nets.

The good news is that the industry kept moving forward. Chips burned in; engineers burned out. But it was still onward and upward.

In the design world, EDA companies devised workarounds to keep designers productive. Test companies innovated as best they could. In the manufacturing sector, foundries found ways to keep one jump ahead of their problems.

While there has always been collaboration across those three functional boundaries - design, test and manufacturing - for the most part problems are addressed within the industry sector that had the primary responsibility for solving the problem

The bad news is that all those "gaps" that have been held at bay for years and years are coming home to roost in a singular challenge: Achieving profitable IC yields at advanced process nodes.

Here's a very short list of high-level challenges for design, test and manufacturing:

Design

• As process nodes shrink, standard deviations and parametric spreads of the process increase. Modeling becomes difficult.
• More complex device structures require extra mask steps - and tighter process control. Sub-wavelength lithography has to been considered by designers when they optimize their designs.
• Transferring chip topography accurately from a designer's workstation to a wafer is much tougher.

Test

• At advanced process nodes, the sheer volume of test data explodes. It has been estimated that test data for a 65nm, 50M-gate chip is about 120 times the amount needed to test a 180nm, 2M-gate chip.
• New defects such as resistive bridging require new tests.
• Traditional stuck-at-fault testing isn't good enough. Overall defect detections and correction is paramount.

Manufacturing

• New materials and more intricate masking steps must be addressed.
• Systematic defects - problems related to spatial- or time-based variations - are appearing at an alarming rate at small process geometries.
• Design, processing and test can all lead to systematic yield problems.

What is striking about these short lists is that most of the high-level problems cross the traditional functional boundaries of design, test, and manufacturing. It's an "organic" problem; unprecedented in its scope - and it requires an unprecedented degree of communication and cooperation.

It is becoming known the industry that achieving profitable yields at advanced process nodes could be as close to a show-stopper as we've seen for quite some time. There's also a consensus on that a multidisciplinary, cross-boundary approach is necessary.

What's missing is a strategic plan.

Conferences such as DesignCon, Wescon, and Semicon have included commendable technical programs this year that emphasize a multidisciplinary, systems-oriented approach. But that's really just a start.

Meeting a challenge of this magnitude and complexity calls for some top-down communications. Here area four modest proposals:

1. Designers who haven't quite made it to the 90nm node - and even some who have - need to hear from their CEOs and from leading lights of the industry that DFT, DFM and design-for-yield are not "nice to haves" but imperatives.
2. Test companies, EDA companies and foundries must to expand and re-energize their technology partnerships.
3. The industry should establish yield enhancement goals and a time line for reaching them, probably under the aegis of ITRA.
4. A clearing house for yield optimization and yield learning should be established so that the industry can have a primary info rmation resource. Learning leads to enhancement. Sharing info rmation at some level will benefit the industry as a whole as well as each of its sectors.

The Yield Learning Report's mission is to promote a better understanding of the relationship between design, test, and manufacturability. It is in this spirit that the four recommendations outlined above are advanced.

Comment and feedback on this article are invited and welcomed. Send email to jshandle@e-contentworks.com