:: Executive Briefings

Five Widely Accepted ATPG Myths

As chip complexity continues its upward spiral, ATPG has responded with innovations that extend the useful life of this time-honored test technology. However, the most productive recent innovation – ATPG compression – is still not well understood.

ATPG compression uses on-chip pattern generators that have some similarities with the on-chip pseudo-random pattern generator (PRPG) circuits used by logic BIST. Not surprisingly, the similarity in terminology has created a few myths about the differences and capabilities of the two technologies.  Jack Shandle interviewed Stephen Pateras of LogicVision to identify these myths of ATPG.

Myth 1: ATPG pattern generators and logic BIST pseudo-random pattern generators perform essentially the same functions.

Fact: Functionality is quite different. ATPG compression uses the on-chip pattern generator as a decompressor. Pre-compressed deterministic patterns are stored in the tester and then sequentially loaded into the on-chip pattern generator that simultaneously decompresses and scans the resulting pattern data into the parallel scan chains.

The pseudo-random test generators of logic BIST, on the other hand, can autonomously create almost any number of random patterns to be scanned into the parallel scan chains. Data is never stored on a tester.

The bottom line in performance terms: An increased number of  parallel scan chains for ATPG compression (compared to ATPG) but unlimited parallel scan chains for logic BIST.

Myth 2. Stuck-at-fault coverage is the best measure of evaluating test methodologies.

Fact: Chip quality depends on overall defect coverage – not just coverage of stuck-at modeled faults. Independent studies show that the large number of random patterns used by logic BIST provides significantly greater defect coverage than the limited number of deterministic patterns used by any variant of ATPG. See Figure 1.

Myth 3: Logic BIST cannot achieve the same level of stuck-at-fault coverage as ATPG because logic BIST uses random pattterns and ATPG uses deterministic patterns.

Fact: While it is true that in many designs an unsophisticated logic BIST implementation would require an unacceptably large number of random patterns to achieve stuck-at-fault coverage, advanced logic BIST offers an effective workaround. Inserting scan-accessed test points into the designs increases testability enough to deliver stuck-at fault coverages comparable to deterministic methods. Typically 50K to 100K random patterns are required – a very reasonable number. Test points also reduce the number of required deterministic patterns.

Myth 4: With compression in its bag of tricks, ATPG now supports at-speed test.

Fact: Both ATPG techniques used for achieving close to at-speed tests are problematic. The "launch-from-shift" technique requires very accurate pin-to-pin timing between the scan enable pin and one or more clock pins. This requires that the scan-enable signal operate at full speed. See Figure 2.

The  “launch-from-capture,” or “double-capture,” technique removes the at-speed scan-enable requirement. But it requires sequential ATPG, which is not only much more CPU intensive than combinational ATPG. This typically results in an unacceptably large number of test patterns.

Logic BIST, on the other hand, operates without any test pin-to-pin timing requirements.  Mature techiques have been developed for on-chip support for at-speed scan-enable signals, multiple asynchronous clocks, and testing logic at clock domain boundaries.

Myth 5: ATPG solutions scale easily with chip size.

Fact: The primary reason for optimism about ATPG’s scalablity is ATPG compression. But it should be noted that the pattern volume reductions are a one time improvement. As design sizes grow, test pattern volumes will become a prob­lem again.

Another challenge is that ATPG tools typically operate on the full flattened netlist. As  a result, changing any part of the design requires a complete regeneration of the deterministic test patterns – obviously with a significant impact on design cycle time. Scaling is possible but it has a penalty. Attempts to address the “flattened netlist” problem by isolating cores with scan cells so they can be dealt with separately often result in prohibitive area overhead.

Commercial logic BIST, on the other hand, makes hierarchical cores self-testable independent of other cores. See Figure 3. Design changes in one core do not affect logic BIST capabilities in other cores. Moreover, patented techniques allow isolation of the core during test using little or no overhead and reuse is possible without modifying the existing logic BIST capabilities.

ATPG has a long history of innovation and will  certainly be around for awhile. Generally speaking, it has the advantage of familiarity and is well understood by test engineers. But ATPG and BIST are not mutually exclusive technologies. In many instances, the tradoffs that are inherent in ATPG can be successfully addressed by employing logic BIST.

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