The Yield Learning Report - Connecting design, test and fab

|  IN THIS ISSUE  |

Executive Briefing: Big Iron to EDA: How LogicVision's Jim Healy stays ahead of industry technology trends

Strategically Speaking: Active Filtering: Making sense of the growing number of DFM and DFY solutions.

Technical Paper: Unified Embedded Test: LogicVision's LV2000 solves the problems of testing SoCs.

In the Media: Recent articles of interest to the IC test and yield learning communities.

Products to Watch: YieldInsight and ScanBurst are two new products from LogicVision that will make it easier to ramp yield and execute DFT.

15 Minutes of Fame

 

:: Welcome to The IC Test and Yield Learning Report Web Site

The IC Test and Yield Learning Report newsletter is produced by LogicVision and its technology partners to promote a better understanding of the relationship between design, test and manufacturability. This site serves as home to the content offered through the newsletter, and is intended to help build the community of those interested in the issues around understanding how semiconductor yields can be improved through actions at every step of the design chain.

Yield learning is defined as the process that takes information feedback from every step in the creation of a new semiconductor chip, and utilizes that information to allow the chip maker to achieve the fastest and highest possible yield for that chip. Information taken at design, debug or manufacturing can be used to learn how to improve yield of the chip or speed the yield enhancement process.

We welcome ideas, comments and contributions from the test and yield learning community.

15 Minutes of Fame

IC Test and Yield Learning Report is a produced by LogicVision, Inc. For more information, please visit www.logicvision.com.